At this year's Optical Fiber Communication Conference (OFC), Co-Packaged Optics (CPO) has become a hot topic among chip manufacturers. Broadcom and Marvell introduced their respective 51.2Tbps switch chips using CPO technology, and Cisco also demonstrated the feasibility of its CPO technology. With the support of CPO technology, a new era for switches is coming! This is a significant advancement for CPO technology and also indicates that the future of using light to move data is indeed bright.

This track has also become a new battlefield for chip giants.

CPO has received a significant boost.

The major driver of this wave of CPO devices is the public cloud providers of data centers. With the emergence of higher bandwidth applications such as AI/ML (Artificial Intelligence/Machine Learning), high-resolution video streams, and virtual reality, network traffic continues to grow, and the pressure on data center networks is also increasing. Companies like Google, Meta, Amazon, Microsoft, or Alibaba have each deployed tens of thousands of switches and are promoting the development of data links from 100GbE to 400GbE and 800GbE at higher speeds, which will consume more power to transmit data through copper cables.

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As the brain of the switch—the switch chip—has had two major long-term development trends over the years:

1. Approximately every two years, the bandwidth of the switch chip will double, which also follows Moore's Law well.

2. To support the increase in the total switch chip bandwidth, the speed, quantity, and power of SerDes are also increasing. The speed of SerDes has increased from 10 Gbit/sec to 112 Gbit/sec, and the number of SerDes around the chip has increased from 64 channels to 512 channels in the 51.2 Tbps generation. The power of SerDes has become a large part of the total system power.

The current solution between switches mostly uses pluggable optical devices, which can be easily replaced or upgraded to higher capacity, but this also means that there are several inches of copper between the switch chip and the optical device interface. Due to the required electrical and optical density, thermal issues, and power consumption, the current pluggable optical devices are also facing the constraint of difficult capacity expansion. As a result, the industry began to explore new methods to improve the efficiency of data centers, and CPO has become a favorable choice!

Co-Packaged Optics (CPO) is a new type of optoelectronic integration technology that encapsulates optical devices (such as lasers, modulators, photodetectors, etc.) at the chip level, directly integrating with the circuits inside the chip, and improving the performance and power efficiency of the communication system through optical interconnection. A key innovation in co-packaging optical devices is to move the optical devices close enough to the Switch ASIC die to remove this extra DSP (see figure below). With CPO, the optical interface in the network switch system changes from a pluggable module at the front end of the switch housing to an optical module packaged in the same package as the switch chip.

Based on this packaging mode, the advantages of CPO technology are fully demonstrated:Enhanced Performance: CPO allows for the direct embedding of optical components into the chip, reducing the distance between the optical components and the internal circuitry of the chip. This minimizes the delay and distortion of electrical signals, thereby improving the performance of the communication system.

Space Saving: CPO can significantly reduce the size of optical modules, especially in high-density data center environments, enabling more ports to be installed in cabinets of the same size.

Reduced Power Consumption: CPO can decrease the steps of energy conversion, thereby reducing power consumption. Compared to traditional optical modules, CPO can reduce power consumption by about 50% at the same data transmission rate.

Improved Reliability: CPO can enhance the interconnect reliability between optics and electronics, and reduce external interference. Moreover, since CPO is packaged at the chip level, it can also improve the reliability of the entire system.

Cost Reduction: CPO can reduce the number of connectors between the chip and the optical module, thereby reducing production costs. In addition, the small size and low power consumption of CPO can also reduce operational costs.

Because of this, more and more chip manufacturers, optical communication companies, and research institutions are actively researching and using optoelectronic co-packaging technology.

The commercial prototype of CPO is emerging in the switch market.

Broadcom

Broadcom entered the optoelectronic field around 1990. In 1995, Broadcom launched its first optoelectronic transceiver, marking the beginning of the company's entry into the optoelectronic field. Since then, Broadcom has made a series of acquisitions, including the acquisition of Epigram, a manufacturer of optical communication equipment, in 1998; the acquisition of Lucent, another optical communication equipment manufacturer, in 2000; and the acquisition of BroadLight, which is engaged in the research and development of optoelectronic devices and modules, in 2016.

It can be said that through continuous acquisitions, Broadcom has further strengthened its R&D capabilities in the optoelectronic field. Broadcom has also developed electronic, optical, and innovative packaging architecture (SCIP™). After years of nurturing, Broadcom is now applying its technological accumulation in the optoelectronic field to switch products.Broadcom discussed its latest switching product at the 2023 Optical Fiber Communication Conference (OFC) — the Broadcom Tomahawk StrataXGS 5, which provides an Ethernet switching capacity of 51.2 Tbps in a single monolithic chip. As shown in the figure below, a notable feature of this switch is that Tomahawk 5 adopts the technology of co-packaging of optics and electronics. It encapsulates the switching chip and the 100G PAM4 interface together, and this new chip can reduce the need for pluggable optical devices that drive signals to the front end of the switch, significantly reducing power consumption. Compared to the 6.4W power of the Tomahawk 4 Humboldt 25.6T, this switch only requires 5.5W of power to supply 800Gbps traffic. Broadcom claims that due to the adoption of co-packaged optics (CPO) technology, the chip can reduce the power required for optical connections by more than 50%.

The 51.2Tbps switch features a new switching chip, which is a 5nm process monolithic chip equipped with six Arm processor cores. The switch also supports features such as VxLAN single channel and PTP and SyncE, providing up to 64 800GbE, 128 400GbE, 256 200GbE, or 512 100GbE links. In fact, these switching chips are designed for switches with speeds above 100GbE. Broadcom stated that a new Tomahawk 5 switch can effectively replace 48 Tomahawk 1 switches from the 2014 era.

In addition to the switching chip, Broadcom also has co-packaged optical transceiver products. It also adopts Broadcom's silicon photonics chip packaging (SCIP™) technology.

Marvell

The Marvell Teralynx 10 switch is another 51.2T switch designed for the 800GbE era. This switch is composed of Marvell's Teralynx 10 51.2 Tbps switching chip and the PAM4 1.6 Tbps optical platform Nova. The Teralynx brand comes from the acquisition of Marvell-Innovium.

The Marvell Teralynx 10 chip, like Broadcom's, is also a programmable 5nm monolithic switching chip with 512 112G SerDes, capable of meeting a wide range of switch configurations such as 32 x 1.6T, 64 x 800G, and 128 x 400G. According to Marvell, a Teralynx 10 replaces 12 of the first generation of 12.8 Tbps, and can reduce power consumption by 80% at the same capacity.

Teralynx 10 uses Teralynx's unique universal ultra-low latency switch and buffering structure, and also supports congestion-aware routing and real-time stream telemetry, enabling the network to automatically adjust and self-heal. With line-rate programmability, new protocols and functions can be added to meet the constantly changing needs of AI/ML. Teralynx 10 supports a wide range of real-time network telemetry, including P4 in-band network telemetry (INT). These features support predictive analysis, faster problem solving, and a higher degree of automation.This new switch chip can reduce the time spent by distributed applications such as AI/ML on the network, maximize computing utilization, and meet the growing bandwidth demands of artificial intelligence and machine learning. It is suitable for leaf-and-spine and backbone applications in next-generation data center networks, as well as AI/ML and high-performance computing (HPC) architectures. Teralynx 10 will be available for sampling in the second quarter.

Cisco

Cisco is also exploring co-packaged optical technology and is collaborating with chip manufacturer Inphi on a CPO-based switch/optical solution for the next-generation 51.2 Tb/s switch and 800 Gb/s pluggable devices, developing joint packaged optical devices (CPO).

At this OFC 2023, Cisco also demonstrated the feasibility of specific steps to implement CPO technology. Cisco pointed out that its Cisco 8111-32EH is a traditional 32-port 2x400G 1RU router, based on the 2x400G-FR4 pluggable optical module (64x400G FR4) of the Cisco Silicon One G100 ASIC. The Cisco CPO router is equipped with a complete set of co-packaged silicon photonics-based optical tiles, driving 64x400G FR4, also based on the Cisco Silicon One G100 ASIC with a CPO substrate. Cisco also invented an innovative method to perform this multiplexer/demultiplexer on the silicon photonics IC. Cisco expects the trial deployment to be carried out simultaneously with the 51.2Tb switch cycle, followed by a larger-scale adoption during the 101.2Tb switch cycle.

Intel

In the field of co-packaged optical technology, Intel is one of the veteran players. In 2015, it announced the launch of its co-package photonic technology. To provide cost-effective interconnect solutions, Intel has been increasing the bandwidth of its silicon photonics and continuously exploring the use of integrated optical devices.

In 2019, Intel acquired Barefoot Networks, an emerging leader in the field of Ethernet switch chips and data center software. In March 2020, Intel demonstrated a co-packaged solution of the 12.8 Tb/s Barefoot Tofino 2 switch and a 1.6 Tb/s integrated photonic engine, with a silicon photonic interconnect platform using a 1.6 Tbps photonic engine, designed and manufactured on the Intel silicon photonics platform, providing four 400GBase-DR4 interfaces. Intel stated that using integrated optical devices can place optical ports near the switch within the same package, thereby reducing power consumption and continuing to expand the switch bandwidth capabilities. Intel also stated that its 51.2 Tb/s solution should be commercially deployable by the end of 2023.

Trials for CPU and GPU manufacturersI believe Intel is not so committed to silicon photonics research just to be able to be connected to new switch chips. It is also unknown whether optical devices can be integrated with CPU, GPU or XPU in the future. We have seen that Intel has spent a lot of effort to support optical interconnection technology through multiple paths. On June 30, 2022, Intel Research demonstrated an eight-wavelength distributed feedback (DFB) laser array fully integrated on a silicon wafer. The array output power uniformity reached +/- 0.25 decibels (dB), wavelength spacing With a uniformity of ±6.5%, this latest optoelectronic co-packaging solution uses dense wavelength division multiplexing (DWDM) technology, showing the prospect of significantly reducing the size of photonic chips while increasing bandwidth. And more importantly, it is designed and manufactured on Intel's commercial 300 mm hybrid silicon photonics platform, so it provides a clear path to mass production of next-generation optoelectronic co-packaging and optical interconnect devices. At the 2022 Intel On Summit, Intel demonstrated another innovation it is developing: a breakthrough in pluggable co-package photonics solutions. Intel researchers have designed a rugged, high-yield, glass-based solution that simplifies manufacturing and reduces costs through a pluggable connector, opening the door to new system and chip packaging architectures in the future. New possibilities. Nvidia also sees the potential of optical interconnects, where interconnected GPUs will benefit from low-latency data transfers and significantly reduced signal losses. Nvidia may implement co-packaged optics on next-generation NVSwitch to enable inter-node communication, and these systems should support approximately 4,000 GPUs in an interconnected NVLink network.   NVIDIA is working together to promote the implementation of this technology. According to Taiwanese media reports, industry sources revealed that TSMC is involved in a research and development project led by Nvidia, which uses its silicon photonics (SiPh) integration technology called COUPE (Compact Universal Photonic Engine) for graphics hardware to combine multiple AI GPU. At the 2023 OFC conference, Ayar Labs demonstrated the industry's first 4 terabits/second (Tbps) bidirectional wavelength division multiplexing (WDM) optical solution. NVIDIA's accelerated computing platform is supported by advanced technologies such as WDM optical interconnect. NVIDIA hopes to provide the "next million-fold" acceleration for AI through optical interconnect. Nvidia also participated in Ayar Labs' Series C round last year, when it raised $130 million to develop its out-of-band lasers and silicon photonics interconnects. Together, the two companies plan to accelerate the development and adoption of optical I/O technology to support the explosive growth of AI and machine learning (ML) applications and data volumes. There are still many challenges in the commercialization of optoelectronic co-sealing technology However, there are several challenges that need to be solved for optoelectronic co-sealing technology to be commercialized on a large scale. It must be reliable, repairable, deployable, significantly energy-saving and cost-effective. While optical interconnects hold the promise of enabling higher levels of bandwidth between chips, especially within data centers, manufacturing difficulties make them prohibitively expensive. Challenge 1: CPO technology relies heavily on silicon photonics technology and requires miniaturization of optical components to fit into ASIC packaging (more than 100 times smaller than traditional QSFP-DD or OSFP modules). We've seen proprietary CPO solutions emerge first from Broadcom, Intel, Marvell and a few other companies, most of which have acquired or partnered with innovative silicon photonics companies. Their accumulation and efforts in this technology have gradually made the commercialization of CPO possible.On the other hand, with the high integration of optics and silicon chips, new engineering capabilities and wafer foundries will be very much needed.

In this regard, GlobalFoundries is a more forward-looking foundry. Since withdrawing from the pursuit of advanced chip processes, GlobalFoundries has been exploring other technologies, and silicon photonics is a technology that GlobalFoundries has placed a big bet on. In 2015, GlobalFoundries acquired a part of IBM Microelectronics, and thus also obtained photonics expertise and intellectual property from IBM Research. In 2016, GlobalFoundries launched its first-generation silicon photonics platform and created an independent silicon photonics business in the same year. At that time, the industry standard for bandwidth was only 40 GB/s. GlobalFoundries bet that the industry would have to use the power of light to move large amounts of data within and between the emerging data centers around the world. It turned out to be true, and now the bandwidth of data centers has reached data rates of 400 GB/s and 800 GB/s.

GF Fotonix is a comprehensive platform for silicon photonics chips created by GlobalFoundries, and it is also the only silicon photonics large-volume 300mm CMOS manufacturing foundry in the industry. According to GlobalFoundries, the platform integrates photonic components with high-performance CMOS logic and RF to achieve a fully integrated monolithic electrical and optical computing and communication engine, while being optimized for low signal loss degradation. In addition, the optical input and optical output of GlobalFoundries' monolithic silicon photonics platform can be achieved through high-density fiber arrays, on-chip integrated lasers, and copper metallization to achieve 2.5D and 3D heterogeneous integration with other semiconductor chips.

Chip giants such as Broadcom, Cisco, Marvell, and NVIDIA, as well as Ayar Labs, Lightmatter, PsiQuantum, Ranovus, and Xanadu in the field of photonic computing, all have close communication and cooperation with GlobalFoundries. In addition, EDA software vendors such as Ansys, Cadence, and Synopsys are also providing design tools for chips and chips based on integrated silicon photonics.

In conclusion, the co-packaging solution of optoelectronics has indeed made a great breakthrough in the new generation of switches compared to the previous generations. However, as mentioned in the text, there are still many factors to overcome for CPO to become mainstream. According to Yole analysts, although CPO has technical advantages, it will be difficult to compete with pluggable modules, and pluggable modules will still be the preferred choice for a long time. Pluggable, OBO, and CPO will coexist for a period of time.

Now, optical devices can be co-packaged with Ethernet switch chips, and in the future, whether it can be integrated with CPUs, GPUs, or XPUs may also be an exploration direction. In the case of insufficient momentum of Moore's Law, the technology of optoelectronic co-packaging is showing its potential, meeting the current booming data processing needs from a new path. Moreover, an important trend is that major chip giants are all deploying, and the technology of optoelectronic co-packaging is coming towards us.