Semiconductor technology continues to evolve and iterate, and MCUs must keep pace with the times. To better embrace future trends, some manufacturers choose to start from the core, such as shifting from the Arm Cortex-M core to the RISC-V core; others opt to integrate AI by adding AI accelerators to the MCU, making it smarter; and there is another approach that this article will mainly introduce, which is the integration of new types of memory.

As a chip that needs to integrate a CPU, SRAM, non-volatile memory, and dedicated peripherals, the most common forms of memory mainly include embedded DRAM, SRAM volatile memory, flash memory, EEPROM non-volatile memory, among which integrated flash memory is an important feature of the MCU. However, as time goes by, flash memory has gradually become one of the bottlenecks that restrict the performance improvement and power consumption reduction of MCUs. On the one hand, the process of flash memory is difficult to extend below 40nm, while MCUs have begun to move towards 28nm, and these storage cells are difficult to integrate into very complex high-k metal gate technologies; on the other hand, the erasable times of the flash memory integrated in automotive MCUs are too few. With each write and erase cycle, the tunnel oxide in the floating gate NOR cell will degrade, and the leakage will increase, thus accelerating the aging of the flash memory, making it unsuitable as a data storage device.

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In addition, although the emergence of flash memory has changed the difficulty of erasing program data brought by ROM in the past, embedded flash memory still requires a long write time, partly because an erase operation must be performed before the write operation, which will cause the main MCU running at two to three orders of magnitude higher than the flash memory to wait for memory access, and these issues may have adverse effects on the performance of the MCU.

Based on the above factors, more and more major MCU manufacturers have begun to choose to integrate new types of memory in the MCU, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), of course, different major manufacturers also have their different choices...

Ultra-low power consumption, Infineon chooses RRAM

MCU giant Infineon has chosen RRAM (ReRAM). On November 25, Infineon announced that it is preparing to introduce TSMC's RAM non-volatile memory (NVM) technology into Infineon's next-generation AURIX MCU with the foundry leader TSMC.

Resistive Random Access Memory, fully known as Resistive Random Access Memory, is referred to as ReRAM or RRAM. As the simplest storage technology in structure, RRAM works by changing the resistance of the dielectric. By applying just the right voltage on the dielectric, fine conductive filaments that allow current flow are generated, and reversible switching between high resistance and low resistance states can be achieved.

Because RRAM can combine the read and write speed of DRAM with the non-volatility of SSD, it has the advantages of high erasability speed, strong durability, and the ability to store multiple bits of data in a single storage cell. Moreover, it has a very important advantage, which is low power consumption. Gary Bronner, Senior Vice President of Rambus Labs, has emphasized that the power consumption of RRAM is much lower than that of flash memory and may be a key differentiating factor for the next generation of MCUs.

In addition, the 2016 paper "Application study: RRAM for Low-Power Microcontrollers" also pointed out that one possible application field of RRAM is as a backup storage device for all volatile memory in the MCU. The paper believes that the energy required to store a bit value in RRAM is less than the energy required to store a bit value in flash memory technology. Each storage cell in RRAM can be set or reset independently of other cells, but in flash memory, it is necessary to erase the entire block first, which increases the workload of data management. Moreover, compared with flash memory, the design of RRAM storage blocks is less complex, high-voltage generators are not required, and the complex structure of transistors with dual gates is replaced by transistors and modified vias. Therefore, RRAM memory seems to be an ideal backup storage device for low-power microcontrollers.The paper also concludes that RRAM, as an additional memory, allows the MCU to quickly enter a very deep sleep mode, thereby completely turning off the power supply, reducing energy leakage to zero, and the time and energy required to store and restore data from RRAM are also very low, and sleep times of less than a minute can even extend the life of the battery and sensor nodes.

From the current technology, RRAM is obviously expected to "turn the spare tire into the main tire", and it can do more than just backup memory in the MCU. Previous data showed that RRAM manufactured with a 65 nm process will help reduce the size of the chip and memory, while consuming only 1/10 of the power compared to flash memory, and what Infineon and TSMC are doing now is to move towards 28nm. It is reported that Infineon and TSMC have been cooperating in RRAM NVM technology for nearly ten years. The official news from Infineon shows that RRAM technology has created a huge potential for performance expansion, power consumption reduction, and cost improvement. It has shipped its AURIX TC4x series samples based on TSMC's 28nm eFlash technology to major customers, and the first batch of samples based on 28nm RRAM technology will be provided to customers by the end of 2023. In a sense, RRAM manufactured with a 28nm process may bring surprises in terms of size, power consumption, and speed.

According to Infineon, AURIX TC3x has become the preferred automotive microcontroller in many application fields, and AURIX TC4x based on TSMC's RRAM technology further expands this success by improving ASIL-D performance, artificial intelligence functions, and the latest network interfaces (including 10Base T1S Ethernet and CAN-XL). The AURIX TC4x MCU combines performance expansion with the latest trends in virtualization, security, and network functions to support the next generation of software-defined vehicles and new E/E architectures, laying the foundation for the introduction of RRAM in the automotive field.

Of course, in addition to low power consumption, cost is also one of the advantages of RRAM. "The future of RRAM: From Embedded Application to In-Memory Computing and Beyond" points out that flash memory at 28nm and below will face the need to add an additional 9-12 mask layers, leading to higher costs, while RRAM, due to its simple memory cell structure and materials, only needs to add one more mask layer to be integrated into the existing manufacturing process, thereby achieving lower production costs.

Fast read and write, ST focuses on PCM

In terms of new storage, STMicroelectronics has always been an early researcher of Phase-Change Memory (PCM) for microcontroller embedded storage, especially for automotive applications. The full name of PCM is Phase-Change RAM (Phase-Change Random Access Memory), which can also be called PCRAM. The principle is to change the temperature to allow the phase change material to switch between low resistance crystalline (conductive) state and high resistance amorphous (non-conductive) state.

The basic mechanism of PCM was invented by Stanford Robert Ovshinsky in the 1960s, made of germanium-antimony-tellurium (GST) alloy, and uses the rapid thermal control changes between the physical properties of the amorphous and crystalline states of the material to read and write at low voltage. Compared with flash memory and other embedded storage technologies, it has many significant advantages, such as low latency, write performance/data retention, long life, low power consumption, high density, good radiation resistance, flexible backend process, and many other technical features.

Perhaps the performance is too excellent, PCM took the lead in the MCU stage. According to pc.watch, in the production technology after the 28-nanometer generation, the first eNVM technology released by the MCU manufacturer is ePCM. In 2018, STMicroelectronics announced that the 28nm FD-SOI automotive MCU technology architecture and performance standards with built-in ePCM began to provide major customers with MCU samples with ePCM.

The news shows that STMicroelectronics is the first company capable of integrating this non-volatile memory with 28nm FD-SOI technology and developing high-performance, low-power automotive MCUs. In fact, STMicroelectronics began researching PCM as early as 2000 and cooperated with Intel. In 2005, STMicroelectronics and Intel jointly developed 90nm PCM technology, and in 2008, the two companies merged their respective discrete memory businesses to establish the Numonyx NV joint venture, which was later acquired by Micron (Boise, Idaho).There was an article that analyzed why Phase Change Memory (PCM) is the most suitable for automotive applications among various eNVM technologies, mainly due to the manufacturability and cost of PCM. For example, in automotive applications, the integration of ePCM storage elements is much cheaper than 28 nm embedded flash memory technology; ePCM provides fast reading and writing, reducing factory programming time and lowering manufacturing costs; it allows for the simulation of true EEPROM's one-bit changeability, significantly reducing system writing time; and provides reliability and durability advantages comparable to embedded flash memory, allowing for more writing...

At present, STMicroelectronics' MCUs equipped with ePCM are mainly used in the automotive field. In 2018, STMicroelectronics stated that ePCM solutions could meet the demand for larger capacity embedded memory in automobiles, with a maximum operating temperature of +165°C, ensuring that the firmware/data can be well preserved after high-temperature reflow soldering process, and are radiation-resistant, providing more security for data. In August 2021, STMicroelectronics began delivering its first batch of Stellar SR6 series automotive MCUs to major car manufacturers, with plans for mass production in 2024. Among them, the Stellar SR6 P and G series of the first batch of MCUs are equipped with up to 20MB of PCM, ensuring excellent read and write performance, long data retention, and compliance with the AEC-Q100 Grade 0 automotive standard.

Flexible use of memory, Renesas chooses MRAM

Among various eNVM technologies, the Japanese MCU giant Renesas has chosen MRAM. MRAM, short for Magnetic RAM, is a technology based on the tunneling magnetoresistance effect, with non-volatile, unlimited read and write cycles, fast writing speed, low power consumption, and high integration with logic chips, among other technical features.

Chief analyst Jim Handy of Objective Analysis once believed that MRAM could store data more persistently than flash memory. He said that one of the characteristics of MRAM and other emerging non-volatile technologies is that programmers can flexibly use memory. Engineers no longer need to limit program code to the size of NOR or restrict data to the size of SRAM, which not only simplifies the design but also saves costs for some customers by allowing the same MRAM-based MCU to be used in various applications.

At present, the mainstream MRAM technology is STT-MRAM (spin-transfer torque MRAM), a variant of MRAM, where the spin of nearby electrons affects the polarity of the MTJ (magnetic tunnel junction). Compared with other forms of MRAM, STT-MRAM has lower power consumption and the ability to further expand. Although STT-MRAM has comparable performance to DRAM and SRAM, such as not losing information even if the power is cut off, and random access like DRAM; the number of erasable and writable times exceeds 10^15, comparable to DRAM and SRAM, far exceeding the 10^5 times of flash memory, it seems to be able to be realized in processes below 10nm. IMEC demonstrated the feasibility of introducing STT-MRAM as the last level (L3) cache memory at the 5nm technology node at the IEEE IEDM conference in 2018. Therefore, many people believe that STT-MRAM will change the traditional computer architecture of "memory (hard disk and NAND flash) as non-volatile, higher-level memory (DRAM and SRAM) as volatile," and is expected to become a leading storage technology.

Renesas focuses on STT-MRAM and continuously develops new technologies for it. At the IEDM 2021 at the end of last year, Renesas announced that it had reduced power consumption and improved write operation speed on a 16nm FinFET logic process embedded STT-MRAM test chip.

Renesas stated that MRAM requires less energy for writing operations than flash memory, making it particularly suitable for applications with frequent data updates. However, as the demand for MCU data processing capabilities soars, the need to balance performance and power consumption also increases, and further reducing power consumption remains an urgent issue. To meet this demand, Renesas has developed two technologies for MRAM, one is the self-terminating write scheme using sloped pulses, and the other is the synchronous write bit optimization technology. Finally, measurements on the 20 Mbit embedded MRAM storage array test chip using 16-nanometer FinFET logic process conducted by Renesas confirmed that the combination of the above two technologies can reduce write energy by 72% and shorten the write pulse application time by 50%.

At the VLSI symposium in June this year, Renesas once again announced that it has developed a circuit technology for STT-MRAM testing, using a 22-nanometer process to manufacture chips with fast read and write operations. Renesas stated that with the continuous advancement of the Internet of Things and artificial intelligence technologies, it is necessary to use more refined process nodes to manufacture MCUs. For processes below 22 nanometers, MRAM manufactured in the back-end of the production line has advantages over flash memory manufactured in the front-end of the production line, because it is compatible with the existing CMOS logic process technology and requires fewer additional masks.Renesas also pointed out that the small read margin of MRAM will reduce the read speed, thereby affecting the performance of the MCU. Therefore, it is necessary to further improve the speed to shorten the system downtime required for wireless (OTA) updates of endpoint devices. To this end, Renesas has developed a fast read technology using a high-precision sensitive amplification circuit, and a fast write technology that optimizes and shortens the mode conversion time by synchronizing the number of write bits. It has been verified that on the test chip, it achieves 5.9 ns random read access and 5.8 MB/s write throughput. Renesas believes that these new technologies have the potential to significantly improve the memory access speed to over 100 MHz, thereby achieving MCUs with higher performance integrated with embedded MRAM.

It is worth mentioning that, unlike Infineon and STMicroelectronics, which are used in automotive electronics, according to official news from Renesas, its MCUs integrated with STT-MRAM technology are mainly used in the field of the Internet of Things at present. As for whether it will turn to the automotive field in the future, we will wait and see.

Emerging Storage, Who Will Be the Future Choice

So, among many emerging storage technologies, who will become the future choice? At present, PCM is definitely at the forefront, after all, the MCU samples integrated with PCM have been shipped, and mass production is also imminent. However, it should be noted that PCM is not a perfect choice, and it also has certain limitations.

Firstly, the cooling process after PCM RESET requires high thermal conductivity, which will bring higher power consumption. Moreover, since its storage principle is to use temperature to achieve the resistance change of phase change materials, it is very sensitive to temperature and cannot be used in a wide temperature range.

Secondly, in order to make phase change materials compatible with CMOS processes, PCM must adopt a multi-layer structure, so the storage density is too low, and it cannot replace NAND Flash in terms of capacity.

Thirdly, due to the typical Ge, Sb, Te element ratio of PCM being 2:2:5, the melting point is relatively low, and there may be a problem that the pre-programmed memory may be erased when it is soldered to the printed circuit board. Although system programming can solve this temperature limit problem, it will also affect the 10-year retention ability at high temperatures.

In fact, the well-known Intel 3D XPoint memory technology is a type of PCM. Due to the excessive number of masks required, the cost is increased, and the manufacturing difficulty is also very difficult. Although this technology has achieved a revolutionary breakthrough in the field of non-volatile memory, it has not escaped the fate of decline.

On the other hand, although MRAM has good performance, the critical current density and power consumption still need to be further reduced. At present, the size of MRAM storage cells is still large and does not support stacking, the process is more complex, large-scale manufacturing is difficult to ensure uniformity, and the storage capacity and yield ramp are slow.Although it was mentioned earlier that IMEC demonstrated the feasibility of introducing STT-MRAM as the last level (L3) cache memory at the 5nm technology node at the 2018 IEEE IEDM conference, this technology has also been proven to be insufficient for extending operations to faster and lower-level caches (L1/L2). On the one hand, compared to SRAM, the writing process of STT-MRAM is still relatively inefficient and time-consuming, imposing an inherent limitation on the switching speed (no faster than 5ns). On the other hand, the speed gain would require an increase in the current flowing through the MTJ, thereby flowing through the thin dielectric barrier, so each read and write operation would cause a small damage to the insulating layer, and over time it would also reduce the durability of the device. Obviously, for L1/L2 cache operations that require sub-nanosecond switching speeds, STT-MRAM is not a good match.

As for RRAM, its shortcomings are also very obvious, the biggest of which is the serious device-level variability. Device-level variability is directly related to the reliability of the chip, but because the state transition of the RRAM device requires controlling the drift and diffusion of oxygen ions under the electric field driven by applying voltage to both electrodes, and the three-dimensional morphology of the conductive filament is difficult to control, coupled with the impact of noise, it is easy to cause device-level variability.

In addition, although RRAM arrays have two structures, the total chip area of the 1T1R structure RRAM depends on the area occupied by the transistor, so the storage density is relatively low; while the Crossbar structure RRAM has a higher storage density, there are voltage drops and sneak paths on the interconnects, causing a decline in read and write performance, an increase in energy consumption, and write interference issues.

In summary, each storage technology has its advantages and disadvantages, and there is no perfect existence. How should MCU manufacturers make trade-offs? How to develop new technologies as much as possible for weaknesses? And how to develop new equipment and new materials needed for emerging technologies? These are all issues that cannot be ignored and need to be considered, but one thing can be confirmed, that is, even MCU manufacturers must pay close attention to the development status and situation of emerging storage technologies, otherwise they will be left behind by competitors.