As semiconductor front-end nodes become increasingly smaller, the cost of design escalates rapidly. Under these circumstances, advanced packaging and its 2.5D and 3D solutions have become crucial and effective in reducing the cost impact associated with front-end manufacturing, while also helping to enhance system performance and provide lower latency, higher bandwidth, and power efficiency.

According to Yole's definition, if a die can integrate more than 16 I/Os per square millimeter with a pitch smaller than 130µm. Some packaging platforms that meet these criteria include ultra-high density (UHD) fan-out, embedded silicon bridges, silicon interposers, 3D stacked memory (such as 3D NAND), high bandwidth memory (HBM), and 3D stacked DRAM.

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Another platform worth considering is 3DSoC, which employs die-to-wafer (D2W) hybrid bonding. There are two possible choices for embedded silicon bridges: the first, known as EMIB, proposed by Intel and embedded in the IC substrate; the second is the silicon interposer embedded in the mold compound, provided by TSMC (LSI) and SPIL (FOEB).

Specifically, in terms of silicon interposers, there are two products: one is traditional or passive, usually provided by TSMC, Samsung, and UMC; the other is active, namely Intel's Foveros. Combining EMIB with Foveros results in Co-EMIB, a technology applied to Intel's Ponte Vecchio processor. Samsung, SK Hynix, and Micron provide 3D stacked DRAM and HBM memory.

It is worth mentioning that Yangtze Memory Technologies (YMT) is the only company to date that uses wafer-to-wafer (W2W) hybrid bonding technology to produce 3D NAND. However, competitors including Kioxia and the aforementioned three companies are considering attacking this technology.

In addition, CIS suppliers such as Sony (since 2015) and OmniVision (since 2022) use W2W hybrid bonding to produce CMOS image sensors, which is also a 3D stacked packaging platform. However, they are not high-end performance platforms because they cannot meet the requirements of I/O density and pitch, representing a significant gap from the aforementioned packaging.

The promising advanced packaging market

Compared with other packaging platforms, the unit quantity of high-performance packaging is small, but due to its complexity, the average selling price is higher, resulting in a higher proportion of revenue generated. It is expected that the revenue will exceed 14.5 billion USD by 2027, higher than 2.6 billion USD in 2022, which means its CAGR from 2022 to 2027 is 41%.This healthy growth is attributed to the increase in high-performance computing end systems, including cloud computing, networking, artificial intelligence, autonomous driving, personal computing, and gaming. These applications all require the production of larger and more complex chips using more sophisticated nodes, which will expand with the increase in cost. These trends have prompted the semiconductor industry to develop system-level scaling strategies with high-end packaging options, rather than just scaling FE advanced nodes.

By breaking down large monolithic SoC dies into smaller chips and only scaling the most critical circuit components, chiplets and heterogeneous integration are an option to reduce scaling costs. This can only be achieved by using 2.5D and 3D integration technologies with high connection density, high bandwidth, and good power efficiency. As a result, due to significant advancements in R&D and production, microbumps, through-silicon vias (TSV), copper pillars, and hybrid bonding are driving IO density and functional integration in high-end performance applications to new heights.

3D SoC (including die-to-wafer and die-to-die heterogeneous packaging) is seen as the next breakthrough for pitch technology below 10µm. As a front-end packaging technology, this enables high-end system-level performance with denser 3D IC stacking of 3D DRAM, heterogeneous integrated packaging, and packaging partition SoC dies. Leading suppliers, especially TSMC, Samsung, and Intel, are targeting this, providing or planning to provide cutting-edge hybrid bonding solutions. This may be the real touch point between the semiconductor and packaging worlds.

Advanced packaging is moving towards the front end. The evidence lies in the foundries and IDMs, as they are becoming the leaders in the market for the most advanced 2.5D and 3D packaging solutions. OSATs are striving to follow this trend, providing innovative advanced packaging solutions to help address the front-end challenges brought about by the slowdown of Moore's Law, but it will be extremely difficult for them to enter the hybrid bonding market, as they lack front-end capabilities and the necessary resources.

Of course, we must also acknowledge that nothing is 100%.

Dissecting the current advanced packaging market

Packaging technology is constantly evolving to meet the increasing demand for chip integration and higher performance for each component. Chip packaging has undergone an evolution from its traditional use. In the traditional use, chip packaging was only used for chip protection. Now, the design choices of packaging play a crucial role in addressing the deceleration of scaling and meeting the diverse needs for high performance.

Smaller footprints and ultra-high wiring are also achieved through 2.5D & 3D heterogeneous packaging technology.

Recently, new players have entered the field of advanced packaging solutions to improve the performance of their high-end products. Various architectures and functions are also used to enhance interconnects between dies. For example, through-silicon vias with vertical connections between dies have become an attractive solution for reducing package size, improving signal integrity, and providing higher data transfer rates in HBM memory. Traditional copper microbumps are used to create short and fast chip-to-chip or chip-to-substrate interconnects. Although it is becoming increasingly difficult to shrink bumps, some manufacturers have introduced a new solution using hybrid bonding to provide direct, higher-density interconnects and scalable interconnect spacing.

Yole has analyzed and compared various packaging solutions that have recently emerged in the advanced packaging market and found that: NVIDIA's A100 uses TSMC's large silicon interposer to connect the GPU and HBM memory, thereby optimizing the footprint and improving component performance; however, the cost of the interposer is relatively high, as more than 50% of the chips in the package correspond to the interposer chips. Faced with these challenges and the cost impact of the silicon interposer process, some manufacturers (such as AMD) use alternative solutions (such as molded interposer) to reduce the size and cost of silicon chips. AMD's MI210 component integrates chips in fan-out elevated bridge technology, where multiple bridge chips connect the processor die to HBM memory. The bridge chips are embedded in the package molding, with HBM and GPU dies stacked on the molded interposer, and copper pillar structures pass through the molding to vertically transmit signals from the dies to the substrate. This solution provides better electrical performance and reduces costs.Apple has also entered the advanced packaging market with its Apple M1 Ultra chip, which connects two processors using a local silicon interposer, marking this technology as ultra-fusion. This novel packaging process includes chip-first processing and redistribution-last processing, which is also the InFO-L process of TSMC. The LPDDR5 memory used in this component is not directly interconnected with the processor chip, but is only integrated at the packaging substrate level.

Facing different challenges in the scaling and interconnection of advanced packaging, hybrid bonding has been introduced as a packaging solution for various semiconductor components.

In 2022, AMD also pioneered the V-Cache technology. It connects the cache chip to the processor using chip-to-wafer hybrid bonding to use additional cache. This enabling technology allows for the vertical stacking of high-speed caches to improve interconnection, reduce bonding spacing, and speed up the processor core's access to high-speed cache. Once the hybrid bonding yield is optimized, this process will provide a more promising solution for 3D packaging.

TSMC plays a crucial role in covering the front end and back end because it has the foundry capability to manufacture advanced nodes for the latest processor chips and provides advanced and complex back-end services that OSAT cannot provide. Heterogeneous solutions enable multiple small chips with different functions and chips from different manufacturing processes to be integrated into a single package. The main goal is to provide a cost-effective integration solution with improved performance, higher transmission speeds, and lower power consumption.

Requirements for equipment and materials

Advanced packaging equipment is as diverse as the existing platform, serving all levels of interconnection, that is, at the level of Si chips (or small chips), Si photonic chips, wiring or redistribution layers (RDL: redistribution layers). It also includes embedded wiring such as embedded bridges or organic interposers, Si interposers, IC substrates, and advanced printed circuit boards (PCBs). At each level, we have seen a trend of reducing interconnection spacing and line spacing (L/S: line space). The complexity of manufacturing these interconnections comes from the various interconnection shapes and materials used to form them. The types of interconnections, manufacturing methods, and equipment used can be distinguished according to the substrate type (wafer or panel) and materials (Si, organic, glass).

Wafer-level packaging (WLP) equipment is relatively mature. This equipment is continuously optimized to address challenges such as cleanliness and temperature control, high aspect ratio features, increased roughness, warpage control, and considerations for various materials in the package.

Wiring on top of the silicon chip and through-silicon vias (TSV) are all made using thin-film technology. For loose L/S, mature MEMS-type equipment can be used to meet the manufacturing needs of core-FO, fan-in, flip-chip, and low-end silicon interposers. For stricter L/S, front-end 300mm equipment from leading equipment manufacturers is used to manufacture BEOL wiring, TSV, or high-end silicon interposers, silicon bridge chips, 3D stacked memory, and 3D SoC. WLP FO (HD and UHD) considers a slightly different approach, where RDL or through-mold vias (TMV: Through-Mold-Vias) are manufactured into the epoxy mold compound (EMC: Epoxy Mold Compound).

After the wiring is completed, the chip is interconnected through hybrid bonding of larger solder bumps, smaller copper pillars, microbumps, or the smallest direct copper pads. Among them, hybrid bonding is a technical turning point for equipment and material suppliers in chip and wafer processing, post-bonding lithography, deposition, thinning and planarization, etching, and plasma cutting, as well as the core of hybrid interconnection.Panel Level Packaging (PLP) equipment and material supply chains are more complex, typically using custom equipment to interconnect on EMC, organic panels, Ajinomoto Build-up Film (ABF), and glass. PLP can utilize subtractive or additive processes, where equipment optimization is often inspired by Surface Mount Technology (SMT), semiconductor, and flat panel display industries to address challenges such as asymmetric warpage, thicker substrates, uniformity of coatings or depositions, thinning, increased roughness, and handling of low-temperature materials. Moreover, due to the lack of panel processing metrology and inspection tools suitable for stringent L/S, PLP process control is difficult. IC substrates and advanced PCBs face the challenge of decreasing interconnect spacing, and we see a shift in technology from SMT to thin films. The interconnect spacing for pick-and-place of embedded bridges and lamination into organic panels becomes more stringent, with RDL-first used for 2.3D organic interposers or Chip-last FO.

In summary, the improvements in WLP and PLP technologies are complementary to the advancements in high-end silicon chips. As a result, we continue to see many exciting developments.