ASML's EUV lithography tools are very expensive. Each EUV tool now approaches $170 million, but you still use many of these tools in leading semiconductor factories. In the future, the cost of each High-NA EUV tool will exceed $350 million. In addition, these wafer fabs also require many DUV lithography tools. Everyone wants a more cost-effective way to pattern chips, as lithography alone accounts for about 35% of the cost at the 3nm process node.

Imagine if there was a way to break this trend.

Last week, Applied Materials, the world's second-largest semiconductor equipment manufacturer, announced that they have a potential solution. The solution is the Centura Sculpta tool, a new tool that can perform a new process step called "pattern shaping."

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According to Applied Materials, the Sculpta tool can be used to reduce the use of EUV lithography for certain layers by as much as half. If true, this would reshape the industry's cost structure. However, the author has significant doubts about Applied Materials' claims, so let's talk about the nuances of this discussion.

In this article, we will delve into the new Centura Sculpta and its related impact.

Firstly, despite a very clear use case, people in the semiconductor and financial industries have a lot of disdain for this tool. Some argue that it is not something new, it is just a very expensive form of inductively coupled plasma used for reactive ion etching, which has existed for decades in high-volume manufacturing. In response, one might also argue that lithography technology has existed for 150 years, and EUV is not something new. Shaping is obviously unique.

Another major rebuttal is that it is immature and still far away. That is also wrong. Although Sculpta was officially announced at SPIE's Lithography and Advanced Patterning conference last week, this new tool has been around for a long time. Since at least 2015, Applied Materials has been publishing public research papers on this type of tool.

Since 2017, the company's first customer has been working with Applied Materials to develop the tool. Applied Materials even gave a technical demonstration at last year's SPIE Advanced Lithography & Patterning conference and provided real customer test data.

Regarding that specific presentation, there is an interesting story. After Applied Materials' presentation, we left the presentation room and talked with some attendees. The consensus was that it was very cool, but it wouldn't work. Why? The company presentations at SPIE are divided into three categories. 1, what is about to go into production, 2, what is years away, planting a stake in the ground, 3, what doesn't work at all but is being presented because there is nothing else related to data. Our assumption last year was that Applied Materials' technology was between care #2 and/or #3.

Now it seems that was a wrong assumption.Applied Material's Centura Sculpta is not a completely immature and production-distant crazy technology. Sculpta is real, it does work, and it will generate hundreds of millions of dollars in revenue in the coming years. Given that it is promoted as directly removing EUV double patterning in the first use case, let's first quickly review the lithography multiple patterning process.

Lithography Multiple Patterning Process

Lithography is the core process of large-scale semiconductor manufacturing. Once the limitations of lithography tools are broken through, you can continue to scale the size of individual features by turning to various multiple patterning schemes. Below is a simplified description of "litho-etch-litho-etch (LELE)", which is one of the most common multiple patterning schemes. For simplicity, we will put other schemes (such as SADP and LELB) in the same bucket as LELE.

The LELE process flow goes through two complete lithography cycles to achieve tighter feature sizes than a single patterning step. The entire cycle can be dozens of different process steps, including the deposition of hard masks, underlayers, mid-layers, SARC, CMP, cleaning, stripping, spinning, baking, developing, exposure, etching, and various metrology/inspection steps in between.

The key is that moving from a single lithography cycle to the LELE process involves double the lithography cost and many other tools involved in the process.

Applied Materials specifically targets the reduction of EUV multiple patterning as the first use case for Sculpta. They claim that they can achieve the same feature fidelity as LELE with a single lithography cycle and Sculpta.

According to Applied Materials, they estimate about 25 kWh per wafer, about 0.5 kg of CO2 equivalent emissions per wafer, and about 15 liters of water consumption per wafer per LE (litho-etch) cycle. In the box on the right, we show the cost. We estimate the capital cost for a monthly start of 100,000 wafers to be about $350 million, and the operating cost per wafer or per EUV cycle per wafer to be about $70. By adopting Applied Materials' new technology, we estimate a saving of about $250 million in capital cost per month per start of 100,000 wafers, and about $50 in manufacturing cost per wafer.

From the above, it can be seen that the cost, electricity, water, and CO2 savings claimed by Applied Materials are huge. TSMC has increased its capacity for the 7-nanometer and 5-nanometer nodes to (approximately) 200,000 wafers per month. Per layer, this will save them $500 million in capital expenditure and over $100 million in annual operating costs.TSMC's 5nm process features EUV (Extreme Ultraviolet) multi-patterning steps. TSMC's 3nm process includes multiple EUV multi-patterning steps. The goal of this technology is to insert a "2nm" node, which may contain more than 10 EUV multi-patterning steps, without the need for Applied Materials' Sculpta pattern shaping. If you assume that Sculpta can be used *everywhere*, then using Sculpta could save *billions of dollars* per year.

However, we need to reiterate that this analysis is overly simplistic, as we cannot use pattern shaping *everywhere*. We will share where and how it is used, but first, let's talk about what Sculpta and pattern shaping are.

What is Centura Sculpta and Pattern Shaping?

At the core of Centura Sculpta is the ability to perform a new type of step called pattern shaping. Pattern shaping involves shooting a ribbon-like plasma beam at the wafer at a certain angle. The angle can be controlled between 0 and 70 degrees compared to the wafer. A zero angle is perpendicular to the wafer at 90 degrees.

The plasma beam moves in a one-dimensional manner to maintain uniform processing on the wafer. The purpose is to unidirectionally extend features in one direction. By rotating the wafer and passing the beam through it again, pattern shaping can be performed in any direction.

It is crucial that pattern shaping does not affect the critical dimensions of silicon features that need to remain unchanged. This means that it is essential to only modify features along one axis. Applied Materials states that they can change a single dimension by 20 length units for every 1 length unit in the other direction.

This is highly selective in direction. Wafer fabs can also control the degree to which the pattern is elongated by increasing or decreasing the time spent bombarding the beam. Etching time is an important lever that wafer fabs can utilize.Another consideration for maintaining shape uniformity is to ensure that the beam angle is optimized for various different structures on the wafer.

If the beam angle is not properly aligned, it may cause shadows on structures of different sizes. If the planarization layer and the hard mask have different etching selectivity, the plasma beam will lead to uneven sidewall straightness. The sidewall profile of the features must be optimized, otherwise there will be issues with performance, power, or yield.

The angle of the plasma beam is very important for the wafer factory to be optimized to ensure that features of various sizes have a uniform and consistent elongation. Using a higher angle with a lower angle will take into account factors such as the time required for etching, the erosion rate of the top layer, and the erosion rate of the bottom layer, in order to maintain the integrity of the critical dimensions. Each application will have a different beam angle and time. Applied Materials has studied a variety of different chemical substances, so the beam can be used for various hard masks, underlayers, and interlayers.

Pattern shaping occurs after the development, cleaning, and etching of photoresist and anti-reflective coatings.Once pattern shaping is achieved, pattern transfer etching can be carried out. This allows for pattern shaping even if you have multiple masks and patterning stages, and pattern shaping can be combined with multiple patterning.

Pattern shaping is not only about developing in the direction of existing features. It can also be performed at any arbitrary angle. To us, this seems to demonstrate more of the alignment and process control of Applied with Sculpta, rather than the actual use cases of asymmetric shaping. We can't think of a use case for asymmetric shaping, but if you think there is one, please share.

Now that we have introduced what pattern shaping is, it's time to introduce the actual use cases of pattern shaping.

Use Cases

The Sculpta tool has three main use cases: tight hole and slot patterns, narrower tip-to-tip patterns, and eliminating stochastic bridging.

The first application is to obtain holes and slot patterns with tight corner-to-corner dimensions using traditional lithography (LE) methods, which requires multiple patterning. With pattern shaping, your advantage is that you can go from one corner to another with just one LE step. Tight corner-to-corner is important because it allows you to pack more functions into the same area. In this case of using through-holes, performance and power characteristics can be improved due to more through-hole areas.

In the above figure, you can see on the left how tight corner-to-corner is achieved using traditional self-aligned LELE technology. You need two different masks to achieve the tight corner-to-corner of the through-holes, but with pattern shaping, you can use one mask to create all through-holes without tight corner-to-corner, and then shape the through-holes to have tight corner-to-corner.

The second application is to produce grooves with tighter tip-to-tip patterns. This is very similar to the first application but with a different type of feature. In this application, pattern shaping is used to bring two sets of lines as close as possible without using a second mask.On the left is the traditional LELE (Line-End-Space) technique. The first mask creates lines, and then the second mask creates a split between them to achieve the tightest possible tip-to-tip spacing. With pattern shaping, you can create 2 sets of lines with a loose trench in between using just one mask. Then, Sculpta can remove as much material as possible to make the trench as thin as possible.

The third application is to reduce random bridging defects. Random bridging defects occur along a line where etching fails to remove all the material it should. Generally, this is because the photoresist layer is not exposed correctly as well.

These defects can increase power by causing electrons to go where they should not. If the bridge eventually connects two critical layers, causing a short circuit or communication error, it can also lead to yield reduction. Applied Materials states that with pattern shaping, Sculpta can reduce these defects by more than 90%.

In various presentations, ASML discussed how scaling down the tip to below 27 nanometers begins to exponentially increase random defects with EUV (Extreme Ultraviolet) single patterning. Pattern shaping will help significantly reduce these pattern defects, as the lithography tool can pattern more relaxed features and Sculpta can shape them into tighter tip-to-tip. Pattern shaping also helps to reduce trench-to-trench defects in the same way.

It should be noted that ASML's data is for simple processes, and the complex wiring used in actual chips would push the defect wall with current resist materials at 30 nanometers or above.

The first use case—Metal Interconnect StackMetal stacking is one of the most critical parts of any process node. It enables the routing of signals around the wafer. The metal stack consists of more than a dozen layers, but the most important layers are M0 to M4. In terms of layout for modern process nodes, M0, M2, and M4 are the key metal layers perpendicular to the gate, while M1 and M3 are parallel to the gate.

The metal stack of a chip is an area that requires many complex and difficult trade-offs. The denser and thinner each metal layer is made, the more signal routing that can be accomplished. Ultimately, this allows for more useful transistors to be installed in any given area. However, this comes at a great cost.

The finer the metal wires made, the higher the resistance of the metal wires. Remember Ohm's law from high school. Ohm's law states R = (V/I), where R is resistance, V is voltage, and I is current. Although Ohm's law is not entirely applicable to such fine wires, process node integration engineers must strive to address the issue of increased circuit resistance due to denser metal layers. They can compensate by increasing voltage or reducing current. The simplified trade-off is that, compared to a looser metal stack, a denser metal stack requires more power to send signals. Shrinking metal spacing is not always a good thing.

Copper is the preferred metal for Intel, TSMC, and Samsung's 3-nanometer and 4-nanometer process nodes. For single patterning EUV, ~32nm is roughly the limit of the current resist chemistry and overlay capabilities for line spacing. For vias, this number is actually higher. For simplicity, assume the limit for EUV single patterning for all features is 30nm.

For demonstration purposes, this example is overly simplified. The image above is a single metal layer on a chip. Each 30nm x 30nm cell that a single patterning EUV tool can define can be copper or an insulator, usually SiO2. This is not how lithography works, but it is easier to explain.

If using EUV single patterning, the metal layer might look like the one above. There are many wires around that transmit signals from one part of the chip to another. These wires also connect to the layers below and above the chip layer we are viewing. In many cases, this layer has vias that pass signals directly up and down to other layers without routing signals. In this example, there is a significant trade-off in resistance due to the metal being only 30 nanometers wide.

This is where multi-patterning comes into play. Its goal is not to fill with more wires, but to maximize the copper area and minimize the SiO2 area. This will achieve lower resistance when sending signals across the entire chip, resulting in higher performance and power efficiency.For simplicity, let's assume that the limit of multi-patterning is now 15 nanometers instead of 30 nanometers. In reality, the current limit for LELE EUV is more in the range of ~21 to ~23nm. The upper limit is TSMC's pitch on the M0 metal layer in its N3E process node. The lower bound is the 2nm node we will discuss later. It should be noted that multi-patterning does not directly halve the pitch, as some margin is sacrificed due to stack overlay errors and randomness.

If our pixel size is now 15nm, using multi-patterning in this overly simplified, demonstrative, and fictitious example, the wiring density would remain the same. Instead, this increase in fidelity would be used to deposit copper proportionally increased relative to SiO2. The copper wire width is increased from 30 nanometers to 45 nanometers, and the tip-to-tip spacing is also improved. The SiO2 insulator still exists to prevent copper signal mixing and short-circuiting the chip.

The increased wire width and tip-to-tip spacing would lead to a significant reduction in resistance and improved power and performance. Please note that the transition from single patterning to SALELE or pattern shaping would not simultaneously improve tip-to-tip and wire spacing. This example is exaggerated and unrealistic, intended to conceptually demonstrate potential benefits.

In the real world, the benefits are smaller but still necessary and are one of the main use cases for pattern shaping. The density of features can already be achieved with single patterning, but the shape of these features cannot. Pattern shaping helps bring the features that lithography can print into the shapes required by the wafer fab.

There are also yield and power trade-offs regarding metal layers and via layers. Vias are the way to connect different metal layers. Each layer is manufactured and then perfectly stacked together. Process margins and overlay determine the ability to stack them perfectly.

Any misalignment can cause one layer to miss the layer below it, so a connection is not established where there should be one (open). Worse still, the metal layer may connect with another layer that should not be connected, resulting in an incorrect connection (short circuit). Since pattern shaping is a selective process, wafer fabs can increase or decrease directional etching in the direction or amount they need to minimize short circuits and open circuits while maximizing feature size.

The resistance issue is very important, especially in the lower vias where pattern shaping is most applicable. At TSMC's N3E node, more than 90% of the via resistance is caused by V0 to V5.In terms of via resistance, the next nine vias are negligible. If the vias from V0 to V5 can be made larger while still fitting within the same area, then the resistance will be reduced without affecting the density.

From a power and performance perspective of the metal stack, the trade-off of better fidelity brought by multi-patterning is good, but from a cost perspective, it takes a big hit. The number of process steps for each metal layer has almost doubled.

Pattern shaping cannot increase the number of metal layers or vias in a given area, but it can increase their size and reduce the tip-to-tip spacing. The first use case is being implemented in a node that will be used for mass production of the metal stack at the end of 2024 / end of 2025.

The next 15 years of EUV lithography

At the same SPIE lithography conference, Martin van den Brink, the long-time Chief Technology Officer of ASML and the driving force behind EUV, gave a keynote and opening speech. In his speech, Martin talked about the past 15 years and the next 15 years of EUV, as well as our direction and ASML's goals.

He compared the effort required to achieve High NA EUV to the initial launch of EUV, which is almost the same, but not as much work is needed. In his presentation, he showed the significant reuse of existing EUV technology, so High NA will be more evolutionary than revolutionary. Obviously, some key components, such as the lens, will be completely new, but there will be more engineering and less pioneering.

He also talked about the target power of 1000 watts, which now seems easier to achieve than previous power improvements. He made some modest jokes about his previous power schedule estimates (which we clearly remember) and caused some laughter from the audience.

Part of the reason for reaching 1000 watts is to achieve 500 wafers per hour, which is important not only in EUV but also in DUV. ASML clearly understands people's concerns about price/productivity, which is particularly focused on high-priced lithography tools.In our view, the focus on productivity for DUV is well deserved, as it remains the mainstay of lithography. Productivity is a key element of ASML's pricing strategy. Increasing throughput is the value proposition for higher pricing. ASML has long used this value-based pricing, supporting the method of increasing pricing by increasing the number of wafers per hour.

We could jest that increasing productivity by one wafer per hour is equivalent to an additional million-dollar pricing, and we might not be far off...

The remainder of Martin's presentation is a wealth of excellent information, facts, and data that go by too quickly to fully comprehend... but are worth a slow replay.

One of the key data points is the power required for each wafer processed through the lithography tool is 100KW (100,000 watts). This is an astonishing figure, as it is not only the laser power but also the ability to accelerate and decelerate the massive granite platform blocks at an astonishing speed as throughput increases.

We have previously noted that the power demand of wafer fabs is an increasingly serious issue. This is why Samsung built its own power plant in Texas, as it could not rely on the unreliable grid there. Another interesting fact not mentioned by Martin is that TSMC consumes about 10% of the entire power grid of Taiwan Island for its wafer fabs!

From this presentation by Martin van den Brink, we have gained new insights into this new tool from Applied Materials.